数据转换器（英文影印版）2010年版

数据转换器（英文影印版）
出版时间：2010年版
内容简介
　　《数据转换器（影印版）》第一本从模拟和数字两种信号处理相结合的角度全面地论述数据转换器的研究生教材。在模拟数字接口技术方面，数字电子技术的进步已经在许多层面上推动了该技术的发展并提供了有效的支持；而关于这些内容的教学的和自学的教材一直是缺失的，这些层面包括：技术规范，转换方法和体系结构，电路设计和测试等。在对必要的背景理论基础进行研究之后，《数据转换器（影印版）》涉及并提供了深入且全面的知识。每章中引导性资料以及众多的实例加强了《数据转换器（影印版）》的广度和深度，大多数实例是以行为仿真的形式给出的。这些例题和章末的习题有助于理解相关内容，有利于使用某些工具进行自我练习，这些工具对培训和设计工作都是很有效的。《数据转换器》对工程技术人士也是一本必不可少的教科书，因为它弥补了本专题的资料缺乏系统化、条理化的不足。《数据转换器（影印版）》设想读者已具备模拟和数字电路的扎实基础；具有使用电路和行为分析的仿真工具的基础。具有统计分析的基础也是有用的，但不是绝对必要的。
目录
Dedication
Preface
1. BACKGROUND ELEMENTS
1.1 The Ideal Data Converter
1.2 Sampling
1.2.1 Undersampling
1.2.2 Sampling-time Jitter
1.3 Amplitude Quantization
1.3.1 Quantization Noise
1.3.2 Properties of the Quantization Noise
1.4 kT/C Noise
1.5 Discrete and Fast Fourier Transforms
1.5.1 Windowing
1.6 Coding Schemes
1.7 The D/A Converter
1.7.1 Ideal Reconstruction
1.7.2 Real Reconstruction
1.8 The Z-Transform
References
2. DATA CONVERTERS SPECIFICATIONS
2.1 Type of Converter
2.2 Conditions of Operation
2.3 Converter Specifications
2.3.1 General Features
2.4 Static Specifications
2.5 Dynamic Specifications
2.6 Digital and Switching Specifications
References
3. NYQUIST-RATE D/A CONVERTERS
3.1 Introduction
3.1.1 DAC Applications
3.1.2 Voltage and Current References
3.2 Types of Converters
3.3 Resistor based Architectures
3.3.1 Resistive Divider
3.3.2 X-Y Selection
3.3.3 Settling of the Output Voltage
3.3.4 Segmented Architectures
3.3.5 Effect of the Mismatch
3.3.6 Trimming and Calibration
3.3.7 Digital Potentiometer
3.3.8 R-2R Resistor Ladder DAC
3.3.9 Deglitching
3.4 Capacitor Based Architectures
3.4.1 Capacitive Divider DAC
3.4.2 Capacitive MDAC
3.4.3 /Flip Around/ MDAC
3.4.4 Hybrid Capacitive-Resistive DACs
3.5 Current Source based Architectures
3.5.1 Basic Operation
3.5.2 Unity Current Generator
3.5.3 Random Mismatch with Unary Selection
3.5.4 Current Sources Selection
3.5.5 Current Switching and Segmentation
3.5.6 Switching of Current Sources
3.6 Other Architectures
References
4. NYQUIST RATE A/D CONVERTERS
4.1 Introduction
4.2 Timing Accuracy
4.2.1 Metastability error
4.3 Full-Flash Converters
4.3.1 Reference Voltages
4.3.2 Offset of Comparators
4.3.3 Offset Auto-zeroing
4.3.4 Practical Limits
4.4 Sub-Ranging and Two-Step Converters
4.4.1 Accuracy Requirements
4.4.2 Two-step Converter as a Non-linear Process
4.5 Folding and Interpolation
4.5.1 Double Folding
4.5.2 Interpolation
4.5.3 Use of Interpolation in Flash Converters
4.5.4 Use of Interpolation in Folding Architectures
4.5.5 Interpolation for Improving Linearity
4.6 Time-Interleaved Converters
4.6.1 Accuracy requirements
4.7 Successive Approximation Converter
4.7.1 Errors and Error Correction
4.7.2 Charge Redistribution
4.8 Pipeline Converters
4.8.1 Accuracy Requirements
4.8.2 Digital Correction
4.8.3 Dynamic Performances
4.8.4 Sampled-data Residue Generator
4.9 Other Architectures
4.9.1 Cyclic (or Algorithmic) Converter
4.9.2 Integrating Converter
4.9.3 Voltage-to-Frequency Converter
References
5. CIRCUITS FOR DATA CONVERTERS
5.1 Sample-and-Hold
5.2 Diode Bridge S&H
5.2.1 Diode Bridge Imperfections
5.2.2 Improved Diode Bridge
5.3 Switched Emitter Follower
5.3.1 Circuit Implementation
5.3.2 Complementary Bipolar S&H
5.4 Features of S&Hs with BJT
5.5 CMOS Sample-and-Hold
5.5.1 Clock Feed-through
5.5.2 Clock Feed-through Compensation
5.5.3 Two-stages OTA as T&H
5.5.4 Use of the Virtual Ground in CMOS S&H
5.5.5 Noise Analysis
5.6 CMOS Switch with Low Voltage Supply
5.6.1 Switch Bootstrapping
5.7 Folding Amplifiers
5.7.1 Current-Folding
5.7.2 Voltage Folding
5.8 Voltage-to-Current Converter
5.9 Clock Generation
References
6. OVERSAMPLING AND LOW ORDER EA MODULATORS
6.1 Introduction
6.1.1 Delta and Sigma-Delta Modulation
6.2 Noise Shaping
6.3 First Order Modulator
6.3.1 Intuitive Views
6.3.2 Use of 1-bit Quantization
6.4 Second Order Modulator
6.5 Circuit Design Issues
6.5.1 Offset
6.5.2 Finite Op-Amp Gain
6.5.3 Finite Op-Amp Bandwidth
6.5.4 Finite Op-Amp Slew-Rate
6.5.5 ADC Non-ideal Operation
6.5.6 DAC Non-ideal Operation
6.6 Architectural Design Issues
6.6.1 Integrator Dynamic Range
6.6.2 Dynamic Ranges Optimization
6.6.3 Sampled-data Circuit Implementation
6.6.4 Noise Analysis
6.6.5 Quantization Error and Dithering
6.6.6 Single-bit and Multi-bit
References
7. HIGH-ORDER, CT EA CONVERTERS AND EA DAC
7.1 SNR Enhancement
7.2 High Order Noise Shaping
7.2.1 Single Stage Architectures
7.2.2 Stability Analysis
7.2.3 Weighted Feedback Summation
7.2.4 Modulator with Local Feedback
7.2.5 Chain of Integrators with Distributed Feedback
7.2.6 Cascaded EA Modulator
7.2.7 Dynamic range for MASH
7.3 Continuous-time EA Modulators
7.3.1 S&H Limitations
7.3.2 CT Implementations
7.3.3 Design of CT from Sampled-Data Equivalent
7.4 Band-Pass EA Modulator
7.4.1 Interleaved N-Path Architecture
7.4.2 Synthesis of the NTF
7.5 Oversampling DAC
7.5.1 1-bit DAC
7.5.2 Double Return-to-zero DAC
References
8. DIGITAL ENHANCEMENT TECHNIQUES
8.1 Introduction
8.2 Error Measurement
8.3 Trimming of Elements
8.4 Foreground Calibration
8.5 Background Calibration
8.5.1 Gain and Offset in Interleaved Converters
8.5.2 Offset Calibration without Redundancy
8.6 Dynamic Matching
8.6.1 Butterfly Randomization
8.6.2 Individual Level Averaging
8.6.3 Data Weighted Averaging
8.7 Decimation and Interpolation
8.7.1 Decimation
8.7.2 Interpolation
References
9. TESTING OF D/A AND A/D CONVERTERS
9.1 Introduction
9.2 Test Board
9.3 Quality and Reliability Test
9.4 Data Processing
9.4.1 Best-fit-line
9.4.2 Sine Wave Fitting
9.4.3 Histogram Method
9.5 Static DAC Testing
9.5.1 Transfer Curve Test
9.5.2 Superposition of Errors
9.5.3 Non-linearity Errors
9.6 Dynamic DAC Testing
9.6.1 Spectral Features
9.6.2 Conversion Time
9.6.3 Glitch Energy
9.7 Static ADC Testing
9.7.1 Code Edge Measurement
9.8 Dynamic ADC Testing
9.8.1 Time Domain Parameters
9.8.2 Improving the Spectral Purity of Sine Waves
9.8.3 Aperture Uncertainty Measure
9.8.4 Settling-time Measure
9.8.5 Use of FFT for Testing
References
Index